Experience Required: 2 - 7 Years
Education Required: • Requires a BS/MS EE or equivalent
• Strong Verilog, SystemVerilog, or C/C++, Perl/shell skills.
• Must have good leadership and communication skills.
• Networking experience is highly desirable, but not required.
• Perform ASIC design and verification of large, complex high-speed ASIC’s for Juniper's next generation of networking products.
• Responsible for block as well as fullchip/multichip verification
• Develop detailed test plans, block and system-level test benches and verification environments; execute and achieve complete coverage to ensure first working silicon.
• Develop functional models for architectural validation.
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development.
• Develop Perl, Tcl and/or shell scripts to enhance current verification infrastructure/methodology.